This report form produces a netlist for PAD's PCB.
Limitations:
This report form works only with Flat designs.
Attribute Where Description
Name Signals The name of each signal net. Bus
signals will be prepended by their
bus name.
Name Devices The name of the device which is used
in the pin list in each signal net.
Value Devices The parts value used for
documentation and silkscreen.
PADS_Part Devices Part name from the PADs library that
matches the DesignWorks part and MUST
be specified. Defines the default
footprint.
PADS_Decal Devices Used to select an alternate footprint
name for a PADs part. Not required.
PADS_Width Signals Signal routing width. Not required.
Ground Devices Non-displayed pins wired to ground.
Power Devices Non-displayed pins wired to Plus5V.
Minus5V Devices Non-displayed pins wired to Minus5V.
Plus12V Devices Non-displayed pins wired to Plus12V.
Minus12V Devices Non-displayed pins wired to Minus12V.
*** IMPORTANT NOTE ***
This netlist script for a third party PCB system is provided with DesignWorks on an "as is" basis with no guarantee that it will work in any particular environment. Capilano Computing has no control over the file formats that may be used by these systems. These scripts have generally been created and tested in conjunction with DesignWorks users and were developed for use with a specific version of the target system. The third party developer may change formats at any time, and we do not have the resources to track every version of every system on the market.
If this script does not appear to generate the format required for your system, we are happy to assist customers in generating the appropriate format. Please contact us at tech@capilano.com and provide a sample netlist and as much information as you can about the required format.
$END
$CHECK(This report form works only for Flat designs) $PURE $PHYSICAL